====== Specifications ======


**Basic**\\
| Processor: | dual core ARM Cortex A9 |
| FPGA: | Xilinx Zynq 7010 SOC |
| RAM:	| 512 MB |
| System memory: | Micro SD up to 32 GB |
| Power consumption (max): | 5 V, 2 A; ±12 V, 1 A |
| Communication interfaces: | RS232, I2C, 1 Gb Ethernet, USB 2.0 |
| Form factor: | Eurocard (160 mm x 100 mm) |

**Fast ADC**\\
| Number of channels: | any 2 of 16 available inputs (selected using multiplexer) |
| Voltage range: | ±1 V / ±10 V software adjustable |
| Sample rate: | 125 MS/s |
| ADC resolution: | 14 bits |
| Input coupling: | DC |
| Bandwidth (-3 dB): | 10 MHz / 50 MHz* |
* if input buffers bypassed by jumpers

**Fast DAC**\\
| Number of channels: | 2 |
| Voltage range: | ±10 V / ±1 V* |
| Sample rate: | 125 MS/s |
| ADC resolution: | 14 bits |
| Bandwidth (-3 dB): | DC - 1 MHz / DC - 50 MHz* |
* if output buffers bypassed by jumpers

**Auxiliary ADC**\\
| Number of channels: | 16, simultaneous sampling |
| Voltage range: | ±10 V |
| Sample rate: | >1 kS/s (depending on configuration) |
| ADC resolution: | 18 bits |
| Input coupling: | DC |
| Oversampling: | 1 - 64 (software adjustable) |

**Auxiliary DAC**\\
| Number of channels: | 16 |
| Voltage range: | ±10 V |
| Sample rate: | >1 kS/s (depending on configuration) |
| DAC resolution: | 16 bits |

**Hi-resolution DAC**\\
| Number of channels: | 3 |
| Voltage range: | ±5 V, ±10 V, 0-5 V, 0-10 V (jumper adjustable) |
| Sample rate: | >30 kS/s (depending on configuration) |
| DAC resolution: | 20 bits |

**Low-resolution ADC**\\
| Number of channels: | 4 |
| Voltage range: | 0 - 3.5 V |
| Sample rate: | 100 kS/s |
| ADC resolution: | 12 bits |
| Input coupling: | DC |

**Digital outputs**\\
| Number of outputs: | 4 + 6 (via IO expander) |
| Voltage level: | 1.8 V / 3.3 V (IO expander) |

**Features**\\
  * Feedback loop for contact and non-contact optical lever based SPM probes
  * Feedback loop for self-sensing probes (e.g. Akiyama) using FM detection via PLL
  * Z piezo signal output through 20-bit DA converter
  * 16 simultaneously sampled 18-bit inputs
  * 16 independent 16-bit outputs
  * Reconfigurable input and output voltage ranges
  * Two lock-in amplifiers with signal generators 500 Hz to 2 MHz
  * Third internal generator for lock-in operation at other than generating frequency
  * Lateral motion control using serial interface or two 20 bit DA converters
  * Variety of ways to perform non-raster and adaptive measurements, including use of Gwyscan library and Lua interface
  * Digital PLL feedback - configurable PLL range up to full range of the lock-in signal generators; configurable lock-in amplitude and phase output filter 100 Hz - 100 kHz SPM modes
  * Atomic Force Microscopy and Force-Distance curves acquisition
  * Magnetic Force Microscopy in the lift mode
  * Conductive AFM, Scanning Thermal Microscopy and other additional signal based SPM methods
  * AM Kelvin Probe Force Microscopy
  * Force Distance curves and Force Volume data acquisition