FPGA

The feedback loop is implemented on a Field Programmable Gate Array (FPGA) that is part of the ZYNQ chip Red Pitaya board. Instead of the FPGA resources provided with Red Pitaya it uses a custom built bitstream, created using Verilog language and Vivado Suite tools from Xilinx. For creating the FPGA bitstream, the tutorials by Anton Potocnik were absolutely invaluable resource (and our capabilities are not yet beyond them).

The main source of data for feedback loop is a 2-channel 14-bit AD converter available on the Red Pitaya board, running at 125 MS/s. The sampled data can  used directly (e.g. in contact mode SPM operation) or passed through two independent lock-in amplifiers to use amplitude (e.g. in tapping mode SPM operation) or phase (e.g. for frequency modulated SPM operation, together with a phase locked loop).

Different digital feedback loops are implemented. The main feedback loop's purpose is to serve as a source of z feedback for SPM measurements.

Other feedback loops can be used to eventually provide PLL feedback for frequency modulated SPM and to maintain the oscillations amplitude constant in tapping mode or frequency modulated SPM. Some other slower feedback loops (e.g. for KPFM) are available in the server, running on the processor side.

Output of the feedback loop can be passed to the microscope using the 2-channel 14-bit DA converter available on the Red Pitaya board, running at 125 MS/s, or using a 20-bit DA converter that is connected directly to the FPGA using SPI interface.